1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device. The invention more particularly relates to a semiconductor device and a method of manufacturing the same having a local interconnection line which connects impurity regions of different conductivity types.
2. Description of the Background Art
A static random access memory (hereinafter simply referred to as "SRAM") is known as one example of a semiconductor device having impurity regions of different conductivity types connected by a local interconnection line. FIG. 69 shows an equivalent circuit diagram of a conventional SRAM of CMOS (Complementary Metal Oxide Semiconductor) type disclosed in Japanese Patent Laying-Open No.2-150062, for example.
As shown in FIG. 69, a memory cell of the SRAM includes two pMOS transistors T1 and T3 for loads, and four nMOS transistors T2, T4, T5 and T6.
The drain of one of a pair of driver nMOS transistors T2 and T4 is connected to the gate electrode of the other transistor, and the drains of PMOS transistors T1 and T3 for loads are respectively connected to the drains of transistors T2 and T4. The sources of driver nMOS transistors T2 and T4 are fixed at a prescribed potential (e.g. ground potential), and supply voltage Vcc is applied to the sources of pMOS transistors T1 and T3 for loads. As a result, current is supplied to a flip-flop circuit constituted of driver nMOS transistors T2 and T4 and pMOS transistors for loads T1 and T3.
Access nMOS transistors T5 and T6 are connected to storage nodes 17a and 17b of the flip-flop circuit described above. The gate electrodes of access nMOS transistors T5 and T6 are connected to a word line 6.
The configuration of the memory cell of the CMOS type SRAM is described in detail using FIG. 70. FIG. 70 is a plan view of a memory cell corresponding to one bit of the CMOS type SRAM.
As shown in FIG. 70, an isolation oxide film 2 is formed in an element isolation region at a major surface of a semiconductor substrate. n.sup.+ impurity regions 11a1, 11a2, 11a3, 11b1, 11b2, and 11b3 are formed in an element formation region surrounded by isolation oxide film 2. p.sup.+ impurity regions 10a1, 10a2, 10b1, and 10b2 are also formed in the element formation region. The n.sup.+ impurity regions 11a1-11b3 form source/drain regions of driver nMOS transistors T2 and T4 and access nMOS transistors T5 and T6. p.sup.+ impurity regions 10a1-10b2 form source/drain regions of load PMOS transistors T1 and T3.
A gate electrode 8 formed of polycrystal silicon, for example, functions as gate electrodes of load PMOS transistor T3 and driver nMOS transistor T4. Gate electrode 8 has an extended portion located in the vicinity of load pMOS transistor T1. A gate electrode 7 functions as gate electrodes of load pMOS transistor T1 and driver nMOS transistor T2, and has an extended portion located in the vicinity of driver nMOS transistor T4. A gate electrode 6 is used as gate electrodes of access nMOS transistors T5 and T6 and as a word line.
An insulating film (not shown) is formed to cover gate electrodes 6-8. Interconnection lines 39a and 39b formed of an aluminum film is formed on the insulating film. p.sup.+ impurity region 10a2, the extended portion of gate electrode 7 and n.sup.+ impurity region 11a2 are connected to each other by interconnection line 39a via contact holes 17a, 16a and 15a formed at the insulating film. p.sup.+ impurity region 10b2, the extended portion of gate electrode 8 and n.sup.+ impurity region 11b2 are connected to each other by interconnection line 39b via contact holes 15b, 16b and 17b formed at the insulating film.
A cross sectional structure along the X1-X2 line of FIG. 70 is described using FIG. 71.
Referring to FIG. 71, a p well 3 and an n well 4 are formed at the major surface of semiconductor substrate 1. n.sup.+ impurity regions 11a2 and 11a3 are formed in p well 3, and p.sup.+ impurity region 10a2 is formed in n well 4.
Sidewall insulating films 9 are formed on sidewalls of gate electrodes 6-8. An interlayer insulating film 12 is formed to cover gate electrodes 6-8. At interlayer insulating film 12, contact hole 15a reaching impurity region 11a2, contact hole 16a reaching gate electrode 7 and contact hole 17a reaching p.sup.+ impurity region 10a2 are formed.
Local interconnection line 39a formed of an aluminum film is formed to extend from the inside of contact holes 15a-17a onto interlayer insulating film 12. An interlayer insulating film 20 is formed to cover interconnection line 39a. A contact hole 21 is formed to reach n.sup.+ impurity region 11a3 through interlayer insulating film 20 and interlayer insulating film 12. An aluminum interconnection line 22 is formed to extend from the inside of contact hole 21 onto interlayer insulating film 20.
As described above, local interconnection line 39a connecting p.sup.+ impurity region 10a2 and n.sup.+ impurity region 11a2 is constituted of a metallic film such as an aluminum film in order to prevent a pn junction from being formed in an interconnection line when impurity regions of different conductivity types are connected.
However, a problem described below arises when a metallic film such as an aluminum film is used as local interconnection line 39a.
Local interconnection 39a is in contact with n impurity region 11a2 via a contact portion 40, in contact with gate electrode 7 via a contact portion 41, and in contact with p.sup.+ impurity region 10a2 via a contact portion 42. Accordingly, impurities in n.sup.+ impurity region 11a3, in p.sup.+ impurity region 10a2, and in gate electrode 7 are sucked up by local interconnection line 39a. A problem in this case is, that contact resistance increases at contact portions 40-42.
Further, there is another problem of generation of leakage current caused by diffusion of a metallic component in local interconnection line 39a into semiconductor substrate 1 at contact portions 40 and 42.
Consequently, a problem of degradation of reliability of the SRAM is caused. The problems described above are not for the SRAM only, but for a semiconductor device having an interconnection line which connects an n type impurity region and a p type impurity region.